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M48Z512A M48Z512AY, M48Z512AV
4 Mbit (512 Kbit x 8) ZEROPOWER(R) SRAM
Features
Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation; unlimited WRITE cycles 10 years of data retention in the absence of power Automatic power-fail chip deselect and WRITE protection Two WRITE Protect voltages: (VPFD = power-fail deselect voltage) - M48Z512A: VCC = 4.75 to 5.5V, 4.5V VPFD 4.75V - M48Z512AY: VCC = 4.5 to 5.5V, 4.2V VPFD 4.5V - M48Z512AV: VCC = 3.0 to 3.6V, 2.8V VPFD 3.0V Battery internally isolated until power is applied Pin and function compatible with JEDEC standard 512K x 8 SRAMs SOIC package provides direct connection for a SNAPHAT top which contains the battery SNAPHAT housing (battery) is replaceable Equivalent Surface-Mount (SMT) solution requires a 28-pin M40Z300/W and a standalone 128K x8 LPSRAM (SNAPHAT(R) top to be ordered separately PMDIP32 is an ECOPACK package
32 1
PMDIP32 (PM) Module
Description
The M48Z512A/Y/V ZEROPOWER(R) RAM is a non-volatile, 4,194,304-bit Static RAM organized as 524,288 words by 8 bits. The devices combine an internal lithium battery, a CMOS SRAM and a control circuit in a plastic, 32-pin DIP Module. For Surface-Mount environments ST provides an equivalent SMT solution consisting of a 28-pin, 330mil SOIC NVRAM Supervisor (M40Z300/W) and a 32-pin, (Type II TSOP, 10 x 20mm) 4Mb LPSRAM. Both 5V and 3V versions are available (see Table 2 on page 7). The unique design allows the SNAPHAT(R) battery package to be mounted on top of the SOIC package after the completion of the surfacemount process. Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel form. The part number is "M4Z32-BR00SH1.

December 2006
Rev 6
1/24
www.st.com 1
Contents
M48Z512A M48Z512AY M48Z512AV
Contents
1 2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 4 5 6 7
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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M48Z512A M48Z512AY M48Z512AV
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Equivalent Surface-Mount (SMT) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 READ mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WRITE mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Down/Up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Down/Up trip points dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PMDIP32 - 32-pin Plastic DIP Module, package mechanical data . . . . . . . . . . . . . . . . . . 18 SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, package mechanical data . . 19 SH - 4-pin SNAPHAT housing for 48mAh battery, package mechanical data . . . . . . . . . . 20 SH - 4-pin SNAPHAT housing for 120mAh battery, package mechanical data . . . . . . . . . 21 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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List of figures
M48Z512A M48Z512AY M48Z512AV
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Hardware hookup for equivalent Surface-Mount (SMT) solution . . . . . . . . . . . . . . . . . . . . . 7 Chip Enable or Output Enable controlled, READ mode ac waveforms . . . . . . . . . . . . . . . . 9 Address controlled, READ mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE Enable controlled, WRITE ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable controlled, WRITE ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power Down/Up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PMDIP32 - 32-pin Plastic DIP Module, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, package outline . . . . . . . . . . 19 SH - 4-pin SNAPHAT housing for 48mAh battery, package outline. . . . . . . . . . . . . . . . . . 20 SH - 4-pin SNAPHAT housing for 120mAh battery, package outline. . . . . . . . . . . . . . . . . 21
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M48Z512A M48Z512AY M48Z512AV
Device overview
1
Device overview
Figure 1. Logic diagram
VCC
19 A0-A18 M48Z512A M48Z512AY M48Z512AV
8 DQ0-DQ7
W E G
VSS
AI02043
Table 1.
Signal names
A0-A18 DQ0-DQ7 E G W VCC VSS Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input WRITE Enable Input Supply voltage Ground
5/24
Device overview Figure 2. DIP connections
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M48Z512A 8 M48Z512AY 9 M48Z512AV 10 11 12 13 14 15 16
M48Z512A M48Z512AY M48Z512AV
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI02044
Figure 3.
Block diagram
VCC
A0-A18
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
512K x 8 SRAM ARRAY
DQ0-DQ7
E W G
INTERNAL BATTERY
VSS
AI02045
6/24
M48Z512A M48Z512AY M48Z512AV Figure 4. Hardware hookup for equivalent Surface-Mount (SMT) solution
Device overview
(2)(3) THS VOUT SNAPHAT BATTERY(4) M40Z300/W E E1CON E2CON E3CON E4CON A RST B BL VSS
VCC 4Mb LPSRAM DQ0-DQ7 E
A0-A18
W VSS
AI03631
1. For pin connections, see individual datasheet for M48Z300/300W at www.st.com. 2. Connect THS pin to VOUT if 4.2V VPFD 4.5V (M48Z512AY) or connect THS pin to VSS if 4.5V VPFD 4.75V (M48Z512A). 3. Connect THS pin to VSS if 2.8V VPFD 3.0V (M48Z512AV). 4. SNAPHAT(R) top ordered separately.
Table 2.
Equivalent Surface-Mount (SMT) solution
NVRAM LPSRAM 5V 4Mb LPSRAM 5V 4Mb LPSRAM 3V 4Mb LPSRAM Supervisor M40Z300 M40Z300 M40Z300W THS pin(1) VSS VOUT VSS
M48Z512A M48Z512AY M48Z512AV
1. Connection of Threshold Select pin (Pin 13) of Supervisor (M40Z300/300W).
7/24
Operating modes
M48Z512A M48Z512AY M48Z512AV
2
Operating modes
The M48Z512A/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance condition. When VCC is out of tolerance, the circuit WRITE protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the switchover voltage (VSO), the control circuitry connects the battery which maintains data until valid power returns. The ZEROPOWER(R) RAM replaces industry standard SRAMs. It provides the nonvolatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Table 3.
Mode Deselect WRITE READ READ Deselect Deselect
Operating modes(1)
VCC 4.75 to 5.5V or 4.5 to 5.5V or 3.0 to 3.6V VSO to VPFD (min)(2) E VIH VIL VIL VIL X X G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery back-up mode
VSO(2)
1. See Table 11 on page 17 for details. 2. X = VIH or VIL; VSO = battery back-up switchover voltage.
2.1
READ mode
The M48Z512A/Y/V is in the READ mode whenever W (WRITE Enable) is high and E (Chip Enable) is low. The device architecture allows ripple-through access of data from eight of 4,194,304 locations in the static storage array. Thus, the unique address specified by the 19 Address Inputs defines which one of the 524,288 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E (Chip Enable) and G (Output Enable) access times are also satisfied. If the E and G access times are not met, valid data will be available after the later of Chip Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain low, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
8/24
M48Z512A M48Z512AY M48Z512AV Figure 5.
Operating modes
Chip Enable or Output Enable controlled, READ mode ac waveforms
tAVAV
A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7
VALID tAXQX tEHQZ
tGHQZ
DATA OUT
AI01221
1. WRITE Enable (W) = high.
Figure 6.
Address controlled, READ mode ac waveforms
A0-A18 tAVAV tAVQV DQ0-DQ7 DATA VALID
AI01220
tAXQX
1. Chip Enable (E) and Output Enable (G) = low, WRITE Enable (W) = high.
9/24
Operating modes Table 4.
Symbol
M48Z512A M48Z512AY M48Z512AV READ mode ac characteristics
Parameter
(1)
M48Z512A/Y -70 Min Max
M48Z512A/Y/V -85 Min 85 Max
Unit
tAVAV tAVQV tELQV tGLQV tELQX(2) tGLQX(2) tEHQZ(2)
READ Cycle Time Address Valid to Output Valid Chip Enable low to Output Valid Output Enable low to Output Valid Chip Enable low to Output Transition Output Enable low to Output Transition Chip Enable high to Output Hi-Z
70 70 70 35 5 5 30 20 5
ns 85 85 45 ns ns ns ns ns 35 25 ns ns ns
5 5
tGHQZ(2) Output Enable high to Output Hi-Z tAXQX Address Transition to Output Transition
5
1. Valid for Ambient Operating Temperature: TA = 0 to 70C or -40 to 85C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. CL = 5pF.
2.2
WRITE mode
The M48Z512A/Y/V is in the WRITE mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable the outputs tWLQZ after W falls.
10/24
M48Z512A M48Z512AY M48Z512AV Figure 7. WRITE Enable controlled, WRITE ac waveforms
tAVAV A0-A18 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
Operating modes
tWHAX
tWHQX
AI01222
1. Output Enable (G) = high.
Figure 8.
Chip Enable controlled, WRITE ac waveforms
tAVAV
A0-A18
VALID tAVEH tAVEL tELEH tEHAX
E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01223
1. Output Enable (G) = high.
11/24
Operating modes Table 5.
Symbol
M48Z512A M48Z512AY M48Z512AV WRITE mode ac characteristics
Parameter
(1)
M48Z512A/Y -70 Min Max
M48Z512A/Y/V -85 Min 85 0 0 65 75 5 15 35 35 0 10 Max
Unit
tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX(2)(3)
WRITE cycle time Address Valid to WRITE Enable low Address Valid to Chip Enable low WRITE Enable pulse width Chip Enable low to Chip Enable high WRITE Enable high to Address Transition Chip Enable high to Address Transition Input Valid to WRITE Enable high Input Valid to Chip Enable high WRITE Enable high to Input Transition Chip Enable high to Input Transition WRITE Enable low to Output Hi-Z Address Valid to WRITE Enable high Address Valid to Chip Enable high WRITE Enable high to Output Transition
70 0 0 55 55 5 15 30 30 0 10 25 65 65 5
ns ns ns ns ns ns ns ns ns ns ns 30 ns ns ns ns
75 75 5
1. Valid for Ambient Operating Temperature: TA = 0 to 70C or -40 to 85C; VCC = 4.75 to 5.5V, 4.5 to 5.5V or 3.0 to 3.6V (except where noted). 2. CL = 5pF. 3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data Retention mode
With valid VCC applied, the M48Z512A/Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, WRITE protecting itself tWP after VCC falls below VPFD. All outputs become high impedance, and all inputs are treated as "don't care." If power fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within the time tWP, WRITE protection takes place. When VCC drops below VSO, the control circuit switches power to the internal energy source which preserves data. The internal coin cell will maintain data in the M48Z512A/Y/V after the initial application of VCC for an accumulated period of at least 10 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. WRITE protection continues for tER after VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume. For more information on battery storage life refer to the Application Note AN1012.
12/24
M48Z512A M48Z512AY M48Z512AV
Operating modes
2.4
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (see Figure 9) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, ST recommends connecting a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface-mount). Figure 9. Supply voltage protection
tAVAV A0-A18 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01223
tELEH
tEHAX
13/24
Maximum rating
M48Z512A M48Z512AY M48Z512AV
3
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Symbol TA TSTG TBIAS TSLD(1)(2) VIO VCC IO PD
Absolute maximum ratings
Parameter Grade 1 Ambient operating temperature Grade 6 Storage temperature (VCC off) Grade 1 Temperature under bias Grade 6 Lead solder temperature for 10 seconds Input or Output voltages M48Z512A/512AY Supply voltage M48Z512AV Output current Power dissipation -0.3 to 4.6 20 1 V mA W -40 to 70 260 -0.3 to 7 -0.3 to 7.0 C V V -40 to 85 -40 to 85 0 to 70 C C Value 0 to 70 C Unit
1. For DIP package: soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). No preheating above 150C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery. 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
Caution:
Negative undershoots below -0.3V are not allowed on any pin while in the battery back-up mode. Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
14/24
M48Z512A M48Z512AY M48Z512AV
DC and ac parameters
4
DC and ac parameters
This section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. The parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and ac measurement conditions(1)
Parameter Supply voltage (VCC) Grade 1 Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and Output timing ref. voltages
1. Output Hi-Z is defined as the point where data is no longer driven.
M48Z512A/512AY 4.75 to 5.5V or 4.5 to 5.5 0 to 70 -40 to 85 100 5 0 to 3 1.5
M48Z512AV Unit 3.0 to 3.6 0 to 70 C -40 to 85 50 5 0 to 3 1.5 pF ns V V V
Grade 6
Figure 10. AC measurement load circuit
DEVICE UNDER TEST
650
CL = 100pF or 30 pF
1.75V
CL includes JIG capacitance
AI03903
1. Excluding open drain output pins; 50pF for M48Z512AV.
Table 8.
Symbol CIN CIO(3)
Capacitance
Parameter(1)(2) Input capacitance Input/Output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5V (M48Z512A/Y) or 3.3V (M48Z512AV); sampled only, not 100% tested. 2. Outputs deselected. 3. At 25C.
15/24
DC and ac parameters Table 9.
Sym
M48Z512A M48Z512AY M48Z512AV DC characteristics
Parameter Test condition(1) M48Z512A/Y -70 Min Max 1 1 115 10 5 -0.3 2.2 IOL = 2.1mA IOH = -1mA 2.4 0.8 VCC + 0.3 0.4 2.2 -0.3 M48Z512AV -85 Min Max 1 1 50 4 3 0.6 A A mA mA mA V V V V Unit
ILI(2)
Input leakage current
0V VIN VCC 0V VOUT VCC E = VIL outputs open E = VIH E VCC - 0.2V
ILO(2) Output leakage current ICC ICC1 ICC2 VIL VIH VOL VOH Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output high voltage
2.2 VCC + 0.3 0.4
1. Valid for ambient operating temperature: TA = 0 to 70C or -40 to 85C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. Outputs deselected.
Figure 11. Power Down/Up mode ac waveforms
tF
VCC VPFD (max) VPFD (min) VSO VSS
tWP tFB
tDR tRB DON'T CARE
tR tER
RECOGNIZED
INPUTS
(Including E)
RECOGNIZED
HIGH-Z OUTPUTS VALID VALID
AI02385
16/24
M48Z512A M48Z512AY M48Z512AV Table 10.
Symbol tF(2) tFB(3) tR tRB tWPT tER
DC and ac parameters
Power Down/Up ac characteristics
Parameter(1) VPFD (max) to VPFD (min) VCC fall time M48Z512A/Y VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time M48Z512A/Y WRITE Protect time M48Z512AV E Recovery time 40 40 250 120 ms M48Z512AV Min 300 10 s 150 10 1 40 150 s s s Max Unit s
1. Valid for ambient operating temperature: TA = 0 to 70C or -40 to 85C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/WRITE protection not occurring until 200s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11.
Symbol
Power Down/Up trip points dc characteristics
Parameter(1)(2) M48Z512A Min 4.5 4.2 2.8 Typ 4.6 4.3 2.9 3.0 2.5 10 Max 4.75 4.5 3.0 Unit V V V V V Years
VPFD
Power-fail deselect voltage
M48Z512AY M48Z512AV M48Z512A/Y
VSO tDR
(3)
Battery back-up switchover voltage M48Z512AV Expected data retention time
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70C or -40 to 85C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted). 3. At 25C; VCC = 0V.
17/24
Package mechanical information
M48Z512A M48Z512AY M48Z512AV
5
Package mechanical information
Figure 12. PMDIP32 - 32-pin Plastic DIP Module, package outline
A
A1 S B e3 D e1
L eA
C
N
E
1 PMDIP
1. Drawing is not to scale.
Table 12.
Symb
PMDIP32 - 32-pin Plastic DIP Module, package mechanical data
mm Typ Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 38.10 14.99 3.05 1.91 32 16.00 3.81 2.79 0.59 0.33 43.18 18.80 2.79 1.50 0.590 0.120 0.075 32 0.630 0.150 0.110 Max 9.52 Typ inches Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 0.023 0.013 1.700 0.740 0.110 Max 0.375
A A1 B C D E e1 e3 eA L S N
18/24
M48Z512A M48Z512AY M48Z512AV
Package mechanical information
Figure 13. SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, package outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
1. Drawing is not to scale.
Table 13.
SOH28 - 28-lead Plastic Small Outline, battery SNAPHAT, package mechanical data
mm inch Max 3.05 0.05 2.34 0.36 0.15 17.70 8.23 1.27 - 3.20 11.51 0.41 0 28 0.10 0.36 2.69 0.51 0.30 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8
Symbol Typ A A1 A2 B C D E e eB H L N CP Min
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Package mechanical information
M48Z512A M48Z512AY M48Z512AV
Figure 14. SH - 4-pin SNAPHAT housing for 48mAh battery, package outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
1. Drawing is not to scale.
Table 14.
Symb
SH - 4-pin SNAPHAT housing for 48mAh battery, package mechanical data
mm Typ Min Max 9.78 6.73 6.48 7.24 6.99 0.38 0.46 21.21 14.22 15.55 3.20 2.03 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ inches Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090
A A1 A2 A3 B D E eA eB L
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M48Z512A M48Z512AY M48Z512AV
Package mechanical information
Figure 15. SH - 4-pin SNAPHAT housing for 120mAh battery, package outline
A1
A2 A A3
eA D
B eB
L
E
SHZP-A
1. Drawing is not to scale.
Table 15.
SH - 4-pin SNAPHAT housing for 120mAh battery, package mechanical data
mm inches Max 10.54 8.00 7.24 8.51 8.00 0.38 0.46 21.21 17.27 15.55 3.20 2.03 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090
Symb Typ A A1 A2 A3 B D E eA eB L Min
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Part numbering
M48Z512A M48Z512AY M48Z512AV
6
Part numbering
Table 16.
Example:
Ordering information scheme
M48Z 512AY -70 PM 1
Device type M48Z
Supply voltage and WRITE Protect voltage 512A = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 512AY = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V 512AV = VCC = 3.0 to 3.6V; VPFD = 2.8 to 3.0V
Speed -70 = 70ns (for M48Z512A/Y) -85 = 85ns (for M48Z512A/Y/V)
Package(1) PM = PMDIP32
Temperature range 1 = 0 to 70C 6 = -40 to 85C
1. The SOIC package (SOH28) requires the battery package (SNAPHAT(R)) which is ordered separately under the part number "M4Zxx-BR00SH" in plastic tube or "M4Zxx-BR00SHTR" in Tape & Reel form.
Caution:
Do not place the SNAPHAT battery package "M4Zxx-BR00SH" in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
Table 17. SNAPHAT battery table
Part number M4Z28-BR00SH M4Z32-BR00SH
Description Lithium battery (48mAh) SNAPHAT Lithium battery (120mAh) SNAPHAT
Package SH SH
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M48Z512A M48Z512AY M48Z512AV
Revision history
7
Revision history
Table 18.
Date March 2000 19-Jul-00 15-Jan-01 19-Dec-01 08-Feb-02 29-May-02 18-Nov-02 17-Sep-03 30-Nov-04 21-Dec-04 22-Feb-05
Revision history
Version 1.0 1.1 1.2 2.0 2.1 2.2 2.3 2.4 3.0 4.0 5.0 First issue M48Z12AV added Changed LPSRAM device (Table 2) Reformatted; added temperature information (Table 4, Table 5, Table 8, Table 9, Table 10, and Table 11); remove chipset option from Ordering Information (Table 16); remove reference to "clock" Remove 85ns speed grade (Table 4, Table 5, and Table 9) Modify reflow time and temperature footnotes (Table 6) Modified SMT text (Figure 1, Figure 4, and Table 2) Remove references to M68xxx (obsolete) part (Figure 4 and Table 2); update disclaimer Reformatted; remove extended temperature references (Table 16) Update Marketing Status for qualification, correct drawing (Figure 4 and Table 16) IR reflow, SO package updates (Table 6) Document reformatted. ECOPACK package text added on coverpage. Note 2 concerning Leaded SOIC package removed below Table 6. Updated PMDIP32 package mechanical data in Section 5: Package mechanical information; updated TA to include Grade 1 (0 to 70C) and Grade 6 (-40 to 85C). Revision Details
21-Dec-2006
6
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M48Z512A M48Z512AY M48Z512AV
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